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MC100LVEP210 Low-Voltage 1:5 Dual Diff. LVECL/LVPECL/LVEPECL/HSTL Clock Driver
The MC100LVEP210 is a low skew 1-to-5 dual differential driver, designed with clock distribution in mind. The LVECL/LVPECL input signals can be either differential or single-ended if the VBB output is used. The signal is fanned out to 5 identical differential outputs. HSTL inputs can be used when the EP210 is operating in LVPECL mode. The LVEP210 specifically guarantees low output-to-output skew. Optimal design, layout, and processing minimize skew within a device and from lot to lot. To ensure the tight skew specification is realized, both sides of the differential output need to be terminated identically into 50 even if only one side is being used. When fewer than all ten pairs are used, identically terminate all the output pairs on the same package side whether used or unused. If no outputs on a single side are used, then leave these outputs open (unterminated). This will maintain minimum output skew. Failure to do this will result in a 10-20ps loss of skew margin (propagation delay) in the output(s) in use. The MC100LVEP210, as with most other LVECL devices, can be operated from a positive VCC supply in LVPECL mode. This allows the LVEP210 to be used for high performance clock distribution in +3.3V or +2.5V systems. Single ended input operation is limited to a VCC 3.0V in PECL mode, or VEE -3.0V in ECL mode. Designers can take advantage of the LVEP210's performance to distribute low skew clocks across the backplane or the board. In a LVPECL environment, series or Thevenin line terminations are typically used as they require no additional power supplies. For more information on using PECL, designers should refer to Application Note AN1406/D.
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32-LEAD TQFP FA SUFFIX CASE 873A
MARKING DIAGRAM*
MC100 LVEP210 AWLYYWW 32 1
A WL YY WW
= Assembly Location = Wafer Lot = Year = Work Week
*For additional information, see Application Note AND8002/D
ORDERING INFORMATION
Device MC100LVEP210FA Package TQFP Shipping 250 Units/Tray 2000 Tape & Reel
* * * * * * * * * * * * * *
100ps Part-to-Part Skew 35ps Output-to-Output Skew Differential Design VBB Output 475ps Typical Propagation Delay High Bandwidth to 1.5GHz Typical LVPECL and HSTL mode: 2.375V to 3.8V VCC with VEE = 0V LVECL mode: 0V VCC with VEE = -2.375V to -3.8V Internal Input Resistors: Pulldown on D, D Pullup and Pulldown on CLK ESD Protection: >2KV HBM, >100V MM Moisture Sensitivity Level 2 For Additional Information, See Application Note AND8003/D Flammability Rating: UL-94 code V-0 @ 1/8", Oxygen Index 28 to 34 Transistor Count = 461 devices
MC100LVEP210FAR2 TQFP
(c) Semiconductor Components Industries, LLC, 1999
1
March, 2000 - Rev. 2
Publication Order Number: MC100LVEP210/D
MC100LVEP210
Qa3 Qa3 Qa4 Qa4 Qb0 Qb0 Qb1 Qb1
24 VCC Qa2 Qa2 Qa1 Qa1 Qa0 Qa0 VCC 25 26 27 28
23
22
21
20
19
18
17 16 15 14 13 VCC Qb2 Qb2 Qb3 Qb3 Qb4 Qb4 VCC PIN CLKn/CLKn
PIN DESCRIPTION
FUNCTION LVECL/LVPECL/HSTL CLK Inputs LVECL/LVPECL Outputs Reference Voltage Output Positive Supply Negative, 0 Supply
MC100LVEP210
29 30 31 32 1 2 3 4 5 6 7 8 12 11 10 9
Qn0:4/Qn0:4 VBB VCC VEE
VCC NC CLKa CLKa VBB CLKb CLKb VEE
Figure 1. 32-Lead TQFP Pinout (Top View)
Warning: All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation. Qa0 Qa0 Qa1 CLKa CLKa Qa1 Qa2 Qa2 Qa3 Qa3 Qa4 Qa4 VBB CLKb CLKb Qb0 Qb0 Qb1 Qb1 Qb2 Qb2 Qb3 Qb3 Qb4 Qb4
Figure 2. Logic Symbol MAXIMUM RATINGS*
Symbol VEE VCC VI VI Iout IBB TA Tstg JA JC Tsol Power Supply (VCC = 0V) Power Supply (VEE = 0V) Input Voltage (VCC = 0V, VI not more negative than VEE) Input Voltage (VEE = 0V, VI not more positive than VCC) Output Current VBB Sink/Source Current{ Operating Temperature Range Storage Temperature Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Solder Temperature (<2 to 3 Seconds: 245C desired) Still Air 500lfpm Continuous Surge Parameter Value -6.0 to 0 6.0 to 0 -6.0 to 0 6.0 to 0 50 100 0.5 -40 to +85 -65 to +150 80 55 12 to 17 265 Unit VDC VDC VDC VDC mA mA C C C/W C/W C
* Maximum Ratings are those values beyond which damage to the device may occur. { Use for inputs of same package only.
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MC100LVEP210
DC CHARACTERISTICS, ECL/LVECL (VCC = 0V; VEE = -3.3(+0.925, -0.5)V) (Note 5.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 1.) Output HIGH Voltage (Note 2.) Output LOW Voltage (Note 2.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference (Note 3.) Min 60 -1145 -1995 -1165 -1810 -1525 -1425 Typ 70 -1020 -1820 Max 90 -895 -1650 -880 -1625 -1325 0.0 150 CLK CLK 0.5 -150 0.5 -150 Min 60 -1145 -1995 -1165 -1810 -1525 -1425 25C Typ 70 -1020 -1820 Max 90 -895 -1650 -880 -1625 -1325 0.0 150 0.5 -150 Min 60 -1145 -1995 -1165 -1810 -1525 -1425 85C Typ 70 -1020 -1820 Max 90 -895 -1650 -880 -1625 -1325 0.0 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 4.) IIH IIL Input HIGH Current Input LOW Current
VEE+1.2
VEE+1.2
VEE+1.2
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 1. VCC = 0V, VEE = VEEmin to VEEmax, all other pins floating. 2. All loading with 50 ohms to VCC-2.0 volts. 3. Single ended input operation is limited VEE -3.0V in ECL/LVECL mode. 4. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 5. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, LVPECL (VCC = 3.3V 0.5V, VEE = 0V) (Note 10.)
-40C Symbol IEE VOH VOL VIH VIL VBB Characteristic Power Supply Current (Note 6.) Output HIGH Voltage (Note 7.) Output LOW Voltage (Note 7.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Output Voltage Reference (Note 8.) Min 60 2155 1305 2135 1490 1775 1.2 1875 Typ 70 2280 1480 Max 90 2405 1650 2420 1675 1975 3.3 150 CLK CLK 0.5 -150 0.5 -150 Min 60 2155 1305 2135 1490 1775 1.2 1875 25C Typ 70 2280 1480 Max 90 2405 1650 2420 1675 1975 3.3 150 0.5 -150 Min 60 2155 1305 2135 1490 1775 1.2 1875 85C Typ 70 2280 1480 Max 90 2405 1650 2420 1675 1975 3.3 150 Unit mA mV mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 9.) IIH IIL Input HIGH Current Input LOW Current
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 6. VCC = 3.3V 0.5V, VEE = 0V, all other pins floating. 7. All loading with 50 ohms to VCC-2.0 volts. 8. Single ended input operation is limited VCC -3.0V in PECL mode. 9. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 10. Input and output parameters vary 1:1 with VCC.
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MC100LVEP210
DC CHARACTERISTICS, LVEPECL (VCC = 2.5V 0.125V, VEE = 0V) (Note 14.)
-40C Symbol IEE VOH VOL VIH VIL Characteristic Power Supply Current (Note 11.) Output HIGH Voltage (Note 12.) Output LOW Voltage (Note 12.) Input HIGH Voltage Single Ended Input LOW Voltage Single Ended Min 60 1355 505 1335 690 1.2 Typ 70 1480 680 Max 90 1605 850 1620 875 2.5 150 CLK CLK 0.5 -150 0.5 -150 Min 60 1355 505 1335 690 1.2 25C Typ 70 1480 680 Max 90 1605 850 1620 875 2.5 150 0.5 -150 Min 60 1355 505 1335 690 1.2 85C Typ 70 1480 680 Max 90 1605 850 1620 875 2.5 150 Unit mA mV mV mV mV V A A
VIHCMR Input HIGH Voltage Common Mode Range (Note 13.) IIH IIL Input HIGH Current Input LOW Current
NOTE: 100EP circuits are designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. The circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500lfpm is maintained. 11. VCC = 2.5V, VEE = 0V, all other pins floating. 12. All loading with 50 ohms to VEE. 13. VIHCMR min varies 1:1 with VEE, max varies 1:1 with VCC. 14. Input and output parameters vary 1:1 with VCC.
DC CHARACTERISTICS, HSTL (VCC = 2.5(-0.125, +1.3)V, VEE = 0V)
-40C Symbol VIH VIL VX Characteristic Input HIGH Voltage Input LOW Voltage Input Crossover Voltage 680 100 Min Typ Max Min 1200 400 900 100 25C Typ Max Min 85C Typ Max Unit mV mV mV mA
ICC Power Supply Current (Note 15.) 100 15. VCC = 2.375V to 3.8V, VEE = 0V, all other pins floating.
AC CHARACTERISTICS (VCC = 0V; VEE = -2.5V to -3.8V) or (VCC = 2.5V to 3.8V; VEE = 0V)
-40C Symbol fmaxLVPECL Characteristic Maximum Toggle Frequency for LVECL and LVPECL (Note 16.) Maximum Toggle Frequency for HSTL (Note 16.) Propagation Delay Differential Within Device Skew Duty Cycle Skew (Note 17.) Cycle-to-Cycle Jitter Input Voltage Swing (Diff.) 150 200 300 TBD TBD TBD 800 1200 150 400 200 Min Typ Max Min 25C Typ 1.5 Max Min 85C Typ Max Unit GHz
fmaxHSTL tPLH, tPHL tSKEW tJITTER VPP
250 350 25 100 TBD 800 1200 150 450 35 300 500 TBD TBD TBD 800 1200 750
MHz ps ps ps mV
tr Output Rise/Fall Times Q 100 170 270 100 180 290 100 280 350 ps tf (20% - 80%) 16. Fmax guaranteed for functionality only. 17. Skew is measured between outputs under identical transitions of similar paths through a device. Duty cycle skew is defined only for differential operation when the delays are measured from the crosspoint of the inputs to the crosspoint of the outputs.
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MC100LVEP210
PACKAGE DIMENSIONS
TQFP FA SUFFIX 32-LEAD PLASTIC PACKAGE CASE 873A-02 ISSUE A
A A1
32 25 4X
0.20 (0.008) AB T-U Z
1
-T- B B1
8
-U- V P DETAIL Y
17
AE
V1 AE DETAIL Y
9
-Z- 9 S1 S
4X
0.20 (0.008) AC T-U Z
G -AB-
SEATING PLANE
DETAIL AD
-AC-
BASE METAL
N
F
8X
D
M_ R
0.20 (0.008)
M
AC T-U Z
0.10 (0.004) AC
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.500 0.700 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.020 0.028 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
J
CE
SECTION AE-AE
X DETAIL AD
GAUGE PLANE
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0.250 (0.010)
H
W
K
Q_
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
-T-, -U-, -Z-
EE EE EE EE
MC100LVEP210
Notes
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MC100LVEP210
Notes
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MC100LVEP210
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MC100LVEP210/D

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